This invention relates to semiconductor devices for information storage. In particular, it relates to vertical thyristors for use in static (SRAM) and dynamic random access memories (DRAM).
Semiconductor thyristor structures for SRAMs and DRAMs, and the processes for manufacturing them are described in several co-pending patent applications commonly assigned to the present assignee. See, e.g. U.S. patent application Ser. No. 14/590,852, entitled “Cross-Coupled Thyristor SRAM Semiconductor Structures and Methods of Fabrication,” issued as U.S. Pat. No. 9,613,968 on Apr. 4, 2017, which is incorporated herein by reference.
Various memory cell designs have been proposed based on the negative differential resistance behavior of a PNPN thyristor. An active or passive gate is often used in these designs for trade-offs among switching speed, retention leakage, or operation voltage. As the size of thyristor memory array cells becomes smaller, the isolation regions between adjoining memory cells also become smaller, reducing the extent of the electrical isolation provided by those regions. In closely spaced thyristors there is the possibility of adjoining cells interfering with each other through capacitive coupling, particularly if they are biased in opposite states. This interference can degrade the performance of the memory array, and in extreme cases even change the state of one of the thyristors.
This invention provides improved isolation between vertical thyristors to reduce cell interference by providing an air gap or a metal conductive shield between the thyristors, thus increasing memory array stability.